
112 - Development of a GNSS Receiver Size Weight & Power Model
DESCRIPTION
In recent years, the design of GNSS receivers has become increasingly complex due to ongoing developments in signal structures and the growing variety of carrier frequencies, bandwidths, waveforms, chipping, and data rates. Based on these parameters and on the advancements in the different application domains, no effective, comprehensive tool currently exists to evaluate the best trade-off in terms of size, weight and power, as well as cost, (SWaP-C) for the design of GNSS receivers (including antenna, front-end, digital signal processor, ASIC, FPGA, etc.).
This lack of predictive modelling leaves designers uncertain about the impact of the different signal and system options/choices on receiver architecture and consequently on SWaP-C characteristics, leading to suboptimal solutions that may not fit the main stakeholder needs of the addressed value chain.
The objective of this activity is to create, validate, and deploy a parametric and flexible and expandable model capable of estimating the SWaP-C metrics of GNSS receivers, based on GNSS signals, system characteristics and application domains. The model will assist system designers in optimizing GNSS receiver architecture, providing key insights into implementation complexity and trade-offs associated with various signal structures, processing options and technologies.
The tasks to be performed shall include:
- State of the Art & Requirements Analysis:
The project will begin with a comprehensive review of current GNSS receiver architectures, including high-volume, commercial products and professional-grade receivers. This review will assess the performance, size, weight, power consumption and costs (SWaP-C) of receivers, including all the components (antenna, front-end, digital stage, etc.). An analysis of the current and future semiconductor roadmaps will be performed to figure out the related computational capacities, power efficiency, available interfaces, and integration capabilities to foster and support the development of new, more-tailored GNSS receivers/products. An analysis of the current and future semiconductor roadmaps will be performed to understand the processing power, efficiency, and integration capabilities available for GNSS receiver development. This step will include trends in ASICs, FPGAs, and general-purpose processors used in signal processing.
- Structural Model Development:
The second task is to establish a general structural model of GNSS receivers for different application domains. This model will incorporate elements such as the antenna, front-end, and digital signal processor, and will account for the Multi-System Constellation Layers. Parametric models will be developed for each sub-system, including frequency bandwidth, sampling rates, signal structure, and different processing features and functionalities. The model will also consider up-to-date semiconductor technologies and future roadmaps.
- Development of SWaP-C Estimation Models:
The 3rd task aims at developing the SWaP-C estimation model and engine for the intended GNSS receiver/solution using the state-of-the-art analysis of Task 1 and the structural model implementation of Task 2. The signal design parameters are the key drivers of the SWaP-C budgets and together with the other configuration parameters will feed the prediction algorithms in charge of performing such assessments.
- Tool Integration and Validation:
The SWaP-C estimation model will be integrated into a user-friendly expert tool. This tool will be validated through comparison with baseline GNSS receivers for specific high-volume, professional, and safety-of-life applications.
The main outputs of the activity will consist of:
- a deliverable SW (a validated expert tool for the SWaP-C characterization of GNSS receivers)
- State-of-the-Art and Requirements Analysis Assessment
- Architectural Model for GNSS Receivers in different application domains
- SWaP-C Estimation Models
- Validation Plan and Testing Results