Agnostic hardware/software codesign framework for GNSS software receiver
This project has the objective to provide HW/SW codesign methodology for GNSS SW receiver application. The methodology is composed of two stages: 1) Architecture Exploration and 2) Architecture Implementation.
The Architecture Exploration phase will be improved to 1) provide a dynamic virtual platform including an ARM Cortex R52 model along with its peripherals and 2) early-stage decision making to guide the system designer using generated monitoring information from the virtual platform. The Architecture Exploration will be extend with the V-model methodology applied on a GNSS application.
The Architecture Implementation phase will be improved to support two different SoC CPU+FPGA platform exportation: 1) Zynq UltraScale+ MPSoC from Xilinx based on the ARM Cortex A53 and Cortex R5 and 2) NG-Ultra platform NanoXplore based on the ARM Cortex R52.
Last Updated: 11/03/2019 13:24